1. Field of the Invention
This invention in general relates to manufacturing of semiconductor. Further this invention is related to manufacturing of VLSI circuits. Further this invention pertains to Semiconductor memory technology such as DRAM, SRAM etc. More particularly this invention encompasses a Yield and Speed Enhancement of Semiconductor Integrated Circuits using Post-Fabrication Transistor Mismatch Compensation Circuitry in Semiconductor memory technology.
2. Description of Prior Art
In semiconductor integrated circuit (IC) manufacturing, there is a typical trade-off between speed and yield. This is even more so when the IC includes analog blocks. For the semiconductor memories such as SRAM and DRAM, the READ access time determines the speed of the memory. The sense amplifier is the most critical analog block in the READ access path. The response speed of the sense amplifier determines the over all speed of the memory. The typical structure of SRAM memory cell with associated bit line capacitance and sense amplifier is shown in FIG. 1. When the cell is accessed, depending on the data stored in the cell, either BL or BL′ starts discharging from the pre charged value of Vdd. Since BL and BL′ lines have very large capacitance, the sense amplifier is used to amplify the small differential signals on these lines and get the rail to rail swing. The high gain sense amplifier needs to be fired at a precise time when the correct differential voltage is developed at its inputs. Otherwise incorrect data could be latched at the output of the memory.
There are two important factors that impact the sense amplifier firing delay. The first one is related to the tracking of the word line and bit line delays across the process corners and the supply voltage fluctuations. The problem becomes worse with the scaling of CMOS technology into the deep sub-micron regime and the associated lower supply voltages. This problem is typically solved by generating the sense control signal by techniques such as replica memory cell.
The second problem relates to the transistor mismatch in the sense amplifier itself. Since the sense amplifier is essentially a differential amplifier, any mismatch in the threshold voltage and the gain factor of the transistors in the two arms of the amplifier shows up as an input offset voltage. In presence of such input offset voltage, the sense amplifier firing signal will have to be further delayed so that the differential voltage developed at the BL and BL′ lines can compensate the offset voltage. Since this problem arises AT THE LOCATION of the signal amplification, it is not possible to predict the offset a-priori, or even track the offset as in the case of bit line delay tracking. So the sense amplifier design is typically done for the worst case offset condition, by delaying the firing signal in order to compensate the offset voltage. This approach will slow down the sense amplifier significantly depending on the magnitude of the mismatch.
As the CMOS technology is scaled to the deep sub micron regime, the random dopant fluctuation effects will increase, thereby making the transistor mismatch worse. If a fab needs a design index of 6σ for yield consideration, the sense amplifier firing will be delayed to cancel the 6σ transistor mismatch. Assuming a normal distribution of transistor mismatch across the wafer lots, the FIG. 2 gives the percentage of sense amplifiers within certain σ value. It should be noted that a 1σ value corresponds to 84% of the devices. In other words, the design index of 6σ implies that for the sake of 16% more devices, 84% of the devices are penalized with respect to the speed. Had it not been for the delayed sense amplifier firing, these 84% of the devices would be in a different higher speed bin, which in turn translates to higher revenue for the fab! At the same time delaying the sense amplifier firing by 1σ value to get high speed IC's means 16% lower yield. When a fab is shipping millions of IC's, 16% lower yield implies a big hit on revenue. Hence in order to get the best of speed and yield, one would require a programmable sense amplifier firing design technique.
Some techniques have been proposed to do offset cancellation of the sense amplifier. However, these suffer from the drawback of slowing down the intrinsic speed of the sense amplifier due to the loading of the output nodes by extra circuitry required for mismatch compensation. Furthermore the mismatch compensation is not to the tune of 100%.
Limitations
Typical 6σ design index for the fab results in slowing down majority of the chips, which are inherently fast due to lower transistor mismatch. In the Deep Sub-Micron technologies, the speed difference will be more than a factor 2 for the 6σ design index versus 1σ design index, i.e. the memory chip which could potentially run at 2 GHz, will have to be marketed with a 1 GHz label.
A manufacturer who likes to be the first to introduce the fastest chips into the market and thereby capture the market can potentially run the fab with 1σ design index. However, the associated loss of yield is enormous which again impacts the bottom line of the fab.
Some of the techniques proposed such as cancellation of sense amplifier offset suffers from the disadvantage of slowing down the inherent response speed of the sense amplifier.